1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method of the same.
2. Description of Related Art
Various MOS transistors have been proposed for high performance MOS transistors, but the current mainstream is a so-called planar transistor including a gate electrode provided on a silicon substrate through a gate insulating film, a source diffusion layer and a drain diffusion layer provided on both sides thereof.
When such a planar transistor is used, an integration density thereof is restricted by the substrate area and the occupied area for element isolation. In addition, an increase in the packaging density of transistors causes an increase in the wiring complexity and the occupied area for wiring, and thus a further increase in the packaging density becomes more difficult. Moreover, for cost reduction, an increase in the substrate diameter is attempted to increase the number of chips to be obtained by one substrate, but further increase in the diameter of a silicon substrate becomes more difficult.
Further, the silicon substrate is of a circular planar shape in the nature of the fabrication method, which has a problem in that when an ordinary rectangular semiconductor chip is fabricated, the circular peripheral edge of the substrate remains unused.
In contrast to such a planar transistor, there is proposed a so-called vertical transistor without a need to use a silicon substrate. For example, Japanese Patent Laid-Open No. 7-297406 discloses a vertical thin film semiconductor device in which a drain electrode, a silicon layer, and a source electrode are laminated in a direction perpendicular to a substrate surface, wherein the drain electrode is formed in contact with the substrate surface, and the drain electrode occupies a wider area than the source electrode.